Archive notice: This article was originally published on January 30, 2008. Links and embedded videos are preserved as part of the historical record.
Energy-efficient chips for mobile devices and high-performance server processors are among the product highlights to be presented at the International Solid State Circuits Conference (ISSCC) http://www.isscc.org/isscc beginning on Sunday. According to published information, chip giant Intel will face strong competition in both the server segment and the mobile field.
For the mobile field, Intel will present a 25-square-millimetre chip using 45-nanometre technology. The processor for mobile internet devices and ultra-mobile PCs is probably the already announced Silverthorne chip. The chip’s power consumption, which is below two watts, was specified in the advance announcement of the ISSCC presentation. Most US media are impressed by this low consumption, but there are exceptions. “The competition finds two watts ridiculous,” the US magazine EETimes quotes market observer Will Strauss as saying. 600 milliwatts should be sufficient for a mobile device.
Texas Instruments (TI) has also announced a mobile-phone chip for the ISSCC that uses 45-nanometre technology. It contains an 840-megahertz processor using ARM11 architecture, supported by a digital signal processor. Although TI announces extensive power-management functions, the precise consumption has not yet been stated. According to EETimes, however, a lower power requirement than Intel’s is likely.
In the server field, Intel will field a quad-core chip from the Itanium family that contains an incredible two billion transistors and is manufactured using 65-nanometre technology. The high-end server chip with which Sun Microsystems will counter at the ISSCC also uses the same feature size. The third-generation processor contains as many as 16 processing cores and runs at 2.3 gigahertz. As the first commercially available chip, the Sun processor also features hardware-based transactional-memory technology. This memory-management model is optimised for parallelised processes in multicore architectures.
