Intel Plans Eight-Core Nehalem Processors

Intel outlines plans for future processors including Nehalem, Dunnington, Tukwila and the Larrabee graphics architecture.

The 45-nanometre Nehalem platform will provide up to eight processing cores and cover systems from notebooks to servers. Initial models are planned to enter production in the fourth quarter of 2008. Dunnington, Intel’s first six-core processor, is expected somewhat earlier for servers. The company is also planning multicore graphics chips under the Larrabee architecture. Research into parallel programming is being advanced with Microsoft at a California university and through work in Germany.

Following the Penryn family introduced in late 2007, Nehalem is Intel’s second generation of 45-nanometre processors and its principal new platform for the mass market. Configurations with at least two and up to eight cores provide scalability, with as many as 731 million transistors per processor. Simultaneous multithreading and a three-level cache hierarchy are intended to improve performance. The family will cover notebooks, desktops and servers, starting with high-end models in the fourth quarter.

Dunnington is expected to arrive earlier during the second half of the year. Intel’s first six-core processor is intended specifically for multiprocessor servers and will expand the Caneland MP platform. The next generation of Itanium server processors is the quad-core Tukwila, described by Intel as the world’s first processor with two billion transistors. US media also expected it later in the year.

Larrabee targets graphics-intensive applications with a high-performance vector-processing unit, a new vector instruction set and a cache design supporting many-core architecture. Intel intends it to compete with graphics products from NVIDIA and AMD, citing software-development tools as an advantage. The schedule was not confirmed. US media suggested late 2009 or early 2010, while Intel had not announced a specific timeline.

Intel is also addressing the unresolved challenge of efficient parallel programming for multicore architectures. “When highly parallel CPUs become available in large volumes, software engineers will have to rethink their approach,” says Intel spokesperson Mike Cato. New programming techniques and specialised compilers will become particularly important for future processors with higher core counts. Intel and Microsoft will fund related research at the University of California, Berkeley. In Germany, Intel is working with research organisations including Forschungszentrum Jülich and universities such as the Technical University of Munich and RWTH Aachen.

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